Infrared communication devices capable of receiving infrared rays have been widely used, such as infrared remote controller receivers. In an infrared communication device, a received infrared transmission code signal is converted into an electric signal by a photodiode, for example, and then amplified. Then, in the infrared communication device, a bandpass filter extracts a predetermined carrier frequently component from the amplified signal, and a carrier detecting circuit determines in accordance with an output signal of the bandpass filter, whether or not a carrier exists, and then outputs a result of the determination.
FIG. 12 is an equivalent circuit diagram showing an arrangement example of a carrier detecting circuit 120. The carrier detecting circuit 120 is provided with a detection circuit 121 which generates a carrier detection level Det from an output signal Sig of the bandpass filter (see FIG. 13); an integration circuit 109 which integrates in accordance with the output Det of the detection circuit 121, a time during which the carrier exists; and a hysteresis comparator 110 which compares an integration output Int of the integration circuit with a threshold level Vt so as to determine whether or not the carrier exists.
The detection circuit 121 is composed of a detector 122 and an integrator 123, and basically performs the following operations. Namely, the detector 122 generates from the output Sig of the bandpass filter, a signal Dett (hereinafter abbreviated to a baseband component Dett) indicating a waveform of a baseband component (not more than 10 kHz) of the output Sig. Further, the integrator 123 compares the baseband component Dett with a reference voltage Vf, and charges and discharges an integration capacitor C102. With this, the carrier detection level Det is generated as a both terminal voltage of the integration capacitor C102. The carrier detection level Det is to be compared to the output Sig of the bandpass filter by the integration circuit 109. Note that, the detection circuit 121 is shown in Japanese Unexamined Patent Publication No. 2002-51093 (Tokukai 2002-51093, published on Feb. 15, 2002; USPN 2002-0098818).
In the detection circuit 121 of the carrier detecting circuit 120, pulses of the carrier frequency to be detected are detected in a group by the detector 122, and the time during which the pulse group exists is integrated by the integrator 123, so that the integration output Int is obtained as the carrier detection level Det. In other words, the detector 122 does not directly generate the carrier detection level Det for the whole receiving system, but is used in the process of generating the carrier detection level Det.
The detector 122 is arranged so as to include a high-speed amplifier 124 which amplifies a difference between the output Sig and the carrier detection level Det at high speed enough to sufficiently respond to the carrier frequency, and outputs a resultant voltage of the amplification; a diode D101 which rectifies the output of the high-speed amplifier 124; a capacitor C101 to which the output voltage of the high-speed amplifier 124 is charged via the diode D101; and a constant current source 125 which discharges the capacitor C101 by a constant current I100.
The integrator 123 is arranged so as to include an amplifier 126 which outputs a current corresponding to a difference between the charged voltage of the capacitor C101 (namely, output Dett of the detector 122) and the predetermined reference voltage Vf from a reference voltage source (not shown); and the integration capacitor C102 which is charged with the output current of the amplifier 126 and which outputs the charged voltage as the carrier detection level Det.
FIG. 13 is waveform charts of the carrier detecting circuit 120 as arranged above. The high-speed amplifier 124 amplifies the difference between the output Sig of the bandpass filter indicated by the reference symbol β1 in FIG. 13 and the carrier detection level Det indicated by the reference symbol β2 in FIG. 13. With this, the capacitor C101 is charged by the action of the diode D101 for a period W1 during which the pulses of the carrier frequency are detected, as indicated by β11 (Dett) and β12 (Vf) in FIG. 13. This raises the output Dett, which is the detection level of the pulse group of the carrier frequency. On the other hand, in a period W2 during which the pulses are not detected, the capacitor C101 is discharged at the current I100 by the constant current source 125 so that the output Dett lowers. As described above, the period W1 is the period during which the pulse group of the carrier frequency to be detected exists as described above, and the integrator 123 integrates the period W1. With this, an integration output of the integrator 123 is the carrier detection level Det indicated by the reference symbol β2 in FIG. 13.
Further, in FIG. 13, the reference symbol α11 indicates the integration output Int of the integration circuit 109 at the following stage, the reference symbol α12 indicates a threshold level of the hysteresis comparator 110, and Dout indicates a digital output signal which is based on the baseband component and demodulated by the hysteresis comparator 110.
Here, the transmission signal of the infrared remote controller is an ASK signal modulated using a carrier whose frequency is from 30 kHz to 60 kHz, and each transmission code has a time length of about 50 msec to 150 msec. Further, in the carrier detecting circuit 120, the detector 122 detects in a group the pulses of the carrier frequency to be detected (30 kHz to 60 kHz as described above), and the integrator 123 integrates the period W1 during which the pulse group exists, so as to obtain the carrier detection level Det as the integration output of the integrator 123.
Therefore the detector 122 is required to operate at high speed enough to sufficiently respond to the carrier frequency. This can cause a capacitance of the capacitor C101 to be comparatively small. On the other hand, the amplifier 126 of the integrator 123 is required to have a response speed with respect to at least a frequency of the baseband component (not more than 10 kHz). Namely, in order to generate the carrier detection level Det based on the baseband component, the integrator 123 needs to have a long time constant of about 100 msec. Consequently, the integration capacitor C102 is required to have a comparatively large capacitance.
It has been generally difficult for the integrator 123 to obtain high response characteristics with respect to a minute current. In these years, however, a chip capable of achieving high response characteristics as well as the time constant of about 100 msec due to a capacitance value that can be integrated (about 100 pF) has been developed as the integrator 123 of the carrier detecting circuit 120.
On the other hand, as more and more infrared communication devices such as the infrared remote controller receivers have come to be mounted on portable information terminals, cutting the cost of the infrared communication devices is highly demanded. In accordance with this, the integration condenser of the carrier detecting circuit, which conventionally has been an external chip condenser (about 0.1 μF), is now become smaller (about 100 pF as described above) and usually built in the integrated circuit as described earlier.
However, even if the condenser can be built in the integrated circuit as described above, the condenser comprises a large portion (about 10 pF to 15 pF/100 μm×100 μm) of the integrated circuit. Thus, miniaturizing the condenser can reduce the chip size, thereby further cutting the cost highly effectively. Here, effective SN separation is required in a carrier detecting circuit including a built-in integration condenser.
FIG. 14 is an electric circuit diagram concretely showing an arrangement of a typical conventional integrator 131 used as the integrator 123. The integrator 131, which is shown in Tokukai 2002-51093, is basically arranged so as to include the integration capacitor C102, a charging circuit 132, and a discharging circuit 133.
The charging circuit 132 is composed of transistors qn101 and qn102 which constitute a differential pair; a constant current source f101; a reference voltage source 134; transistors qn103 and qp101 which takes out an output from the differential pair; transistors qp103 and qp104 which constitute a current mirror circuit and mirrors an output current from the transistor qp101; a transistor qp102 which inputs to the integration capacitor C102, an output current from the transistor qp104; and transistors qp105 and qp106 which constitute a leak photocurrent compensating circuit as shown in, for example, Japanese Unexamined Patent Publication No. 3-262153 (Tokukaihei 3-262153; published on Nov. 21, 1991).
On the other hand, the discharging circuit 133 is composed of transistors qn104 and qn105 which constitute a differential pair; constant current sources f102 and f103; transistors qp107 and qp108 which constitute a current mirror circuit and mirrors an output current from the transistor qn104; a transistor qn106 which outputs as the carrier detection level Det, an output from the transistors qp108 and qn105; and transistors qp109 and qp110 which constitute a leak photocurrent compensating circuit.
In the integrator 131 as arranged above, if the voltage charged to the capacitor C101, namely the output Dett of the detector 122, is lower than the reference voltage Vf from the reference voltage source 134, the transistor qn102 is switched ON. This consequently switches ON the transistors qn103, qp101, qp103, qp104 and qp102, so that the integration capacitor C102 is charged by a charge current Icj. Note that, since the discharging circuit 133 discharges the integration capacitor C102 by a discharge current Icf, the charge current Icj is a current obtained by subtracting the discharge current Icf from a charge current from the transistor qp102.
Here, the following expression is satisfied.Icj=i101/hfe(qn103)−i102/hfe(qn104),  (1)
where i101 is a constant current that the constant current source f101 draws from the emitters of the transistors qn101 and qn102; i102 is a constant current that the constant current source f102 draws from the emitters of the transistors qn104 and qn105; and hfe (qn103) and hfe (qn104) are current amplification ratios of the transistors qn103 and qn104, respectively.
On the other hand, if the output Dett is higher than the reference voltage Vf, the transistor qn 102 is switched OFF. This consequently switches OFF the transistors qn103, qp101, qp103, qp104 and qp102. Therefore the integration capacitor C102 is not charged from the transistor qp102 but only discharged by the discharge current Icf.
Therefore the following expression is satisfied.Icf=i102/hfe(qn104)  (2)
If it is assumed as typical values that i101=30 nA, i102=30 nA, hfe (qn)=150, and C102=100 pF, then Icj=100 pA, Icf=100 pA, and a charge and discharge time constant is 100 msec/0.1 V in accordance with t=CV/I. In this case, a charge and discharge current ratio (Icj/Icf) is 1, and it is possible to receive a signal whose transmission code has a duty ratio of 50%.
Here, in order to further reduce the capacitance of the integration capacitor C102 for the cost reduction, it is necessary to reduce both the operating currents i101 and i102 of the differential pairs while substantially maintaining the above time constant.
However, if the operating currents i101 and i102 are low currents of not more than 10 nA, the following problems may occur. Namely, the impedance of the transistors in the charge and discharging circuits increase to such an extent that the circuits cannot operate normally. Further, influence of process variation and temperature dependence become significant.
In other words, an input and output resistance of a single transistor increases as a corrector current Ic decreases. This is expressed by the following expressions.Input resistance: rπ=hfe*Vt/Ic  (3)Output resistance: ro=Va/Ic  (4)Note that, Vt=k*T/q (k: Boltzmann constant, T: absolute temperature, q: elementary charge of electron), and Va is Early voltage.
In order to halve the capacitance of the integration capacitor C102 to 50 pF, it is necessary to decrease each of the operating currents i101 and i102 to 15 nA. Here, in the discharging circuit 133, in particular, the collector currents of the transistors qn104 and qn105 have to be i102/2=7.5 nA. As a result, the foregoing problems occur.